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APL5912
0.8V Reference Ultra Low Dropout (0.2V@5A) Linear Regulator
Features
* * * * * * * * * * * * * * * Ultra Low Dropout - 0.2V (typical) at 5A Output Current Low ESR Output Capacitor (Multi-layer Chip Capacitors (MLCC)) Applicable 0.8V Reference Voltage High Output Accuracy - 1.5% over Line, Load and Temperature Fast Transient Response Adjustable Output Voltage by External Resistors Power-On-Reset Monitoring on Both VCNTL and VIN Pins Internal Soft-Start Current-Limit Protection Under-Voltage Protection Thermal Shutdown with Hysteresis Power-OK Output with a Delay Time Shutdown for Standby or Suspend Mode Simple SOP-8-P Package with Exposed Pad Lead Free Available (RoHS Compliant)
General Description
The APL5912 is a 5A ultra low dropout linear regulator. This product is specifically designed to provide well supply voltage for front-side-bus termination on motherboard and NB applications. The IC needs two supply voltages, a control voltage for the circuitry and a main supply volatege for power conversion, to reduce power dissipation and provide extremely low dropout. The APL5912 integrates many functions. A Power-OnReset (POR) circuit monitors both supply voltages to prevent wrong operations. A thermal shutdown and current limit functions protect the device against thermal and current over-loads. A POK indicates the output status with time delay which is set internally. It can control other converter for power sequence. The APL5912 can be enabled by other power system. Pulling and holding the EN pin below 0.3V shuts off the output. The APL5912 is available in SOP-8-P package which features small size as SOP-8 and an Exposed Pad to reduce the junction-to-case resistance, being applicable in 2~3W applications.
Pin Configuration
GND FB VOUT VOUT
1 2 3 4 8
Applications
* * * Front Side Bus VTT (1.2V/5A) Note Book PC Applications Motherboard Applications
VIN
7 6 5
EN POK VCNTL VIN
SOP-8-P (Top View) = Exposed Pad (connected to VIN plane for better heat dissipation)
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APL5912
Ordering and Marking Information
APL5912 Lead Free Code Handling Code Temp. Range Package Code Package Code KA : SOP-8-P Operating Ambient Temp. Range C : 0 to 70C Handing Code TU : Tube TR : Tape & Reel Lead Free Code L : Lead Free Device Blank : Original Device XXXXX - Date Code
APL5912 KA :
APL5912 XXXXX
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature.
Block Diagram
EN
VCNTL
VIN
PowerOn-Reset Soft-Start and Control Logic
UV
Thermal Limit
0.4V
VREF 0.8V
EAMP
VOUT FB
POK 90% VREF
Current Limit
Delay
GND
POK
Typical Application Circuit
1. Using an Output Capacitor with ESR18m
C CNTL 1uF VCNTL +5V VIN +1.5V
6
R3 1k
POK
7
VCNTL POK VIN VOUT VOUT
5
CIN 100uF
3 4
A PL5912
EN
8
C OUT
2
VOUT +1.2V / 5A
220uF R2 2k R1 1k C1 33 nF (in the range of 12 ~ 48nF)
EN GND
1
FB
Enable
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APL5912
Typical Application Circuit (Cont.)
2. Using an MLCC as the Output Capacitor
C CNTL 1uF
R4 10 (in the range of 5.1~15 )
VCNTL +5V VIN +1.5V
6
R3 1k
POK
7
VCNTL POK VIN VOUT VOUT
5
CIN 22uF
3 4
COUT
2
VOUT +1.2V / 5A
APL5912
EN
8
22uF R1 39k C1 30pF
EN GND
1
FB
Enable
R2 78k
VOUT(V) 1.05 1.5 1.8
R1 (k) 43 27 15
R2 (k) 137.6 30.86 12
C1 (pF) 27 36 68
Absolute Maximum Ratings
Symbol VCNTL VIN VI/O VPOK PD PPEAK TJ TSTG TSDR VESD Parameter VCNTL Supply Voltage (VCNTL to GND) VIN Supply Voltage (VIN to GND) EN and FB to GND POK to GND Average Power Dissipation Peak Power Dissipation (<20mS) Junction Temperature Storage Temperature Soldering Temperature, 10 Seconds Minimum ESD Rating (Human Body Mode) Rating -0.3 ~ 7 -0.3 ~ 3.3 -0.3 ~ VCNTL+0.3 -0.3 ~ 7 3 20 150 -65 ~ 150 300 2 Unit V V V V W W
o o o
C C C
kV
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APL5912
Thermal Characteristics
Symbol JA
Note : JA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of SOP-8-P is soldered directly on the PCB.
Parameter Junction-to-Ambient Thermal Resistance in Free Air (Note)
Value 40
Unit
o
C/W
Recommended Operating Conditions
Symbol VCNTL VIN VOUT IOUT TJ VOUT Output Current Junction Temperature Parameter VCNTL Supply Voltage VIN Supply Voltage Output Voltage VCNTL=3.35% VCNTL=5.05% 0.8 ~ 1.2 0.8 ~ VIN-0.2 0~6 -25 ~ 125 V A
o
Range 3.1 ~ 6 1.1 ~ 3.3
Unit V V
C
Electrical Characteristics
Refer to the typical application circuit. These specifications apply over, VCNTL = 5V, VIN = 1.5V, VOUT = 1.2V and TA = 0 to 70C, unless otherwise specified. Typical values refer to TA = 25C.
Symbol
Parameter
Test Conditions
APL5912 Min Typ Max
Unit
SUPPLY CURRENT ICNTL ISD VCNTL Nominal Supply Current VCNTL Shuntdown Current VCNTL POR Threshold VCNTL POR Hysteresis VIN POR Threshold VIN POR Hysteresis VIN Rising 0.8 EN = VCNTL EN = GND VCNTL Rising 2.7 0.4 1 180 2.9 0.4 0.9 0.5 1.0 8 300 3.1 mA A V V V V
POWER-ON-RESET
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APL5912
Electrical Characteristics (Cont.)
Refer to the typical application circuit. These specifications apply over, VCNTL = 5V, VIN = 1.5V, VOUT = 1.2V and TA = 0 to 70C, unless otherwise specified. Typical values refer to TA = 25C.
Symbol OUTPUT VOLTAGE VREF
Parameter
Test Conditions
APL5912 Min Typ 0.8
o
Max
Unit
Reference Voltage Output Voltage Accuracy Line Regulation Load Regulation
FB =VOUT IOUT=0A ~ 5A, TJ= -25 ~125 C VCNTL=3.3 ~ 5V IOUT=0A ~ 5A IOUT = 5A, VCNTL=5V, TJ= 25oC IOUT = 5A, VCNTL=5V, TJ= -25~125 C VCNTL=5V, TJ= 25 C
o o
V +1.5 % % % V V A A A A
o o
-1.5
0.06 0.15 0.06 0.15 0.15 0.2 0.25 7
o
DROPOUT VOLTAGE Dropout Voltage PROTECTION 8 7.8 150 50 VFB Falling 0.3 0.4 0.4 30 EN=GND 10 2 0.5 9 8.8 VCNTL=5V, TJ= -25 ~ 125 C VCNTL=3.3V, TJ= 25 C VCNTL=3.3V, TJ= -25 ~ 125 C TSD Thermal Shutdown Temperature Thermal Shutdown Hysteresis Under-Voltage Threshold ENABLE and SOFT-START EN Logic High Threshold Voltage VEN Rising EN Hysteresis EN Pin Pull-Up Current TSS Soft-Start Interval POWER OK and DELAY POK Threshold Voltage for VPOK Power OK POK Threshold Voltage for VPNOK Power Not OK POK Low Voltage TDELAY POK Delay Time V mV A mS TJ Rising
o o
ILIM
Current Limit
6 6.8 6
C
C
V
VFB Rising VFB Falling POK sinks 5mA
90% 92% 94% VREF 79% 81% 83% VREF 0.25 1 3 0.4 10 V mS
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APL5912
Typical Operating Characteristics
VCNTL Supply Current vs. Junction Temperature
1.0
8.6
Current-limit vs. Junction Temperature
VOUT=1.2V
VCNTL Supply Current, ICNTL (mA)
0.9 0.8 0.7 0.6 0.5
VCNTL=5V
8.4
Current-limit, ILIM (A)
8.2 8 7.8 7.6
VCNTL=5V
VCNTL=3.3V
0.4 0.3 0.2 0.1 0.0 -50 -25 0 25 50 75 100 125
VCNTL=3.3V
7.4 7.2 7 -50
-25
0
25
50
75
100
125
Junction Temperature (C)
Junction Temperature (C)
Dropout Voltage vs. Output Current
250 200
Dropout Voltage vs. Output Current
VCNTL=5V
VOUT=1.2V Dropout Voltage (mV)
200
VCNTL=3.3V TJ=125C
VOUT=1.2V
TJ=125C
Dropout Voltage (mV)
TJ=75C
150
150
TJ=75C TJ=25C
TJ=25C
100
100
TJ=0C TJ=-25C
TJ=0C
50
50
TJ=-25C
0 0 1 2 3 4 5
0 0 1 2 3 4 5
Output Current, lOUT(A)
Output Current, lOUT(A)
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APL5912
Typical Operating Characteristics
Reference Voltage vs. Junction Temperature
0.808
POK Delay Time vs. Junction Temperature
4.5 4.3 4.1
Referemce Voltage, VREF (mV)
0.806 0.804 0.802 0.800 0.798 0.796 0.794 0.792 -50 -25 0 25 50 75 100 125
POK Delay Time (ms)
3.9 3.7 3.5 3.3 3.1 2.9 2.7 2.5 -50 -25 0
VCNTL=5V
VCNTL=3.3V
25
50
75
100
125
Junction Temperature (C)
Junction Temperature (C)
VCNTL PSRR
0.00 -10.00
0
VIN PSRR
VCNTL = 5V VIN = 1.5V(lower bound) VINPK-PK = 100mV -10 CIN = 47F COUT = 330uF(30m ohm) IOUT = 5A -20 VOUT = 1.2V
-30
Ripple Rejection (dB)
-20.00 -30.00 -40.00 -50.00 -60.00 -70.00
VCNTL = 4.5V~5.5V VIN = 1.5V VOUT = 1.2V IOUT = 5A CIN = 100F COUT = 330uF(ESR=30m)
Amplitude (dB)
-40
-50
-60
100
1000
10000
100000
1000000
100
1000
10000
100000
1000000
Frequency (Hz)
Frequency (Hz)
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APL5912
Operating Waveforms
Test Circuit
R4 C2 1uF
5
2.2
L1 1uH
+5V
R8 8.2k C8 470pF
7 VCC BOOT OCSET 2 8 1
D1 1N4148
C3 1uF
C4 470uFx2
C9 47uF CVCNTL 1uF
VC N T L +5V POK
6
Q3
UGATE PHASE
C6 0.1uF
Q1 A P M 2 0 1 4 N L2 3.3uH
V IN +1.5V C5 1000uFx2
VCNTL
5
Shutdown
VIN
POK VOUT
7
R3 1k
U2 APW7057
6 FB GND 4 LGATE
Q2 APM2014N
CIN 100uF
3 4
VOUT + 1 . 2 V 5A /
C OUT 220uF
R5 1.75k
EN
8
U1 APL5912
EN GND
1
VOUT
FB
2
1. Load transient Response
1.1 Using an Output Capacitor with ESR18m
- COUT = 220F/6.3V (ESR = 30m), CIN = 100F/6.3V - IOUT = 10mA to 5A to 10mA, Rise time = Fall time = 1 S
IOUT = 10mA -> 5A
3
Enable
R2 2k
R1 1k
C1 33nF
R7 2k C7 0.1uF R6 0
IOUT = 10mA -> 5A ->10mA
R1=1k, R2=2k, C1=33nF
IOUT = 5A -> 10mA
1
VOUT
1
VOUT
1
VOUT
IOUT
IOUT IOUT
2
2
2
Ch1 : VOUT, 50mV/Div Ch2 : IOUT, 2A/Div Time : 2S/Div
Ch1 : VOUT, 50mV/Div Ch2 : IOUT, 2A/Div Time : 20S/Div
Ch1 : VOUT, 50mV/Div Ch2 : IOUT, 2A/Div Time : 2S/Div
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APL5912
Operating Waveforms (Cont.)
1.2 Using an MLCC as the Output Capacitor
- COUT = 22F/6.3V (ESR = 3m), CIN = 22F/6.3V - IOUT = 10mA to 5A to 10mA, Rise time = Fall time = 1S
IOUT = 10mA -> 5A IOUT = 10mA -> 5A ->10mA
R1=39k, R2=78k C1=30pF
IOUT = 5A -> 10mA
1
VOUT
1
VOUT
VOUT
1
IOUT
IOUT IOUT
2
2
2
Ch1 : VOUT, 100mV/Div Ch2 : IOUT, 2A/Div Time : 2S/Div
Ch1 : VOUT, 100mV/Div Ch2 : IOUT, 2A/Div Time : 20S/Div
Ch1 : VOUT, 100mV/Div Ch2 : IOUT, 2A/Div Time : 2S/Div
2. Power ON / Power OFF : - VIN = 1.5V, VCNTL = 5V,VOUT = 1.2V - COUT = 220F/6.3V (ESR = 30m), CIN = 100F/6.3V, RL = 1
Power ON
VIN Ch1 VOUT Ch2 VCNTL VPOK Ch3 Ch4
Ch3 Ch4 VOUT Ch2 VCNTL VPOK Ch1 VIN
Power OFF
Ch1 : VIN,1V/div Ch2 : VOUT,1V/div Ch3 : VPOK,1V/div Ch4 : VCNTL,2V/div Time : 10ms/div
Ch1 : VIN,1V/div Ch2 : VOUT,1V/div Ch3 : VPOK,1V/div Ch4 : VCNTL,2V/div Time : 10ms/div
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APL5912
Operating Waveforms (Cont.)
3. Shutdown and Enable : - VIN = 1.5V, VCNTL = 5V, VOUT = 1.2V - COUT = 220F/6.3V (ESR = 30m), CIN = 100F/6.3V, RL = 1
Shutdown
Ch1 VEN
Ch1
Enable
VEN
VOUT Ch2
Ch2
VOUT
IOUT Ch3 VPOK Ch4
Ch4 Ch3
IOUT VPOK
Ch1 : VEN,5V/div Ch2 : VOUT,1V/div Ch3 : IOUT,1A/div Ch4 : VPOK,1V/div Time : 1ms/div
Ch1 : VEN,5V/div Ch2 : VOUT,1V/div Ch3 : IOUT,1A/div Ch4 : VPOK,1V/div Time : 1ms/div
4. POK Delay : - VIN = 1.5V, VCNTL = 5V, VOUT = 1.2V - COUT = 220F/6.3V (ESR = 30m), CIN = 100F/6.3V, RL = 1
VIN Ch1 POK Delay VOUT Ch2
VPOK Ch3
Ch1 : VIN,1V/div Ch2 : VOUT,1V/div Ch3 : VPOK,1V/div Time : 1ms/div
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APL5912
Functional Pin Description
GND (Pin 1) Ground pin of the circuitry. All voltage levels are measured with respect to this pin. FB (Pin 2) Connecting this pin to an external resistor divider receives the feedback voltage of the regulator. The output voltage set by the resistor divider is determined by : R1 VOUT = 0.8 1 + (V) R2 where R1 is connected from VOUT to FB with Kelvin sensing and R2 is connected from FB to GND. A bypass capacitor may be connected with R1in parallel to improve load transient response. The recommended R2 and R1 are in the range of 100~10k. VOUT (Pin 3,4) Output of the regulator. Please connect Pin 3 and 4 together using wide tracks. It is necessary to connect a output capacitor with this pin for closed-loop compensation and improving transient responses. VIN (Pin 5) and Exposed Pad Main supply input pins for power conversions. The Exposed Pad provide a very low impedance input path for the main supply voltage. Please tie the Exposed Pad and VIN Pin (Pin 8) together to reduce the dropout voltage. The voltage at this pins is monitored for PowerOn Reset purpose. VCNTL (Pin 6) Power input pin of the control circuitry. Connecting this pin to a +5V (recommended) supply voltage provides the bias for the control circuitry. The voltage at this pin is monitored for Power-On Reset purpose. POK (Pin 7) Power-OK signal output pin. This pin is an open-drain output used to indicate status of output voltage by sensing FB voltage. This pin is pulled low when the rising FB voltage is not above the VPOK threshold or the falling FB voltage is below the VPNOK threshold, indicating the output is not OK. EN (Pin 8) Enable control pin. Pulling and holding this pin below 0.3V shuts down the output. When re-enabled, the IC undergoes a new soft-start cycle . Left this pin open, an internal current source 10A pulls this pin up to VCNTL voltage, enabling the regulator.
Functional Description
Power-On-Reset A Power-On-Reset (POR) circuit monitors both input voltages at VCNTL and VIN pins to prevent wrong logic controls. The POR function initiates a soft-start process after the two supply voltages exceed their rising POR threshold voltages during powering on. The POR function also pulls low the POK pin regardless the output voltage when the VCNTL voltage falls below it' falling POR threshold. s Internal Soft-Start An internal soft-start function controls rise rate of the output voltage to limit the current surge at start-up. The typical soft-start interval is about 2mS. Output Voltage Regulation An error amplifier working with a temperature-compensated 0.8V reference and an output NMOS regulates output to the preset voltage. The error amplifier designed with
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APL5912
Functional Description (Cont.)
Output Voltage Regulation (Cont.) high bandwidth and DC gain provides very fast transient response and less load regulation. It compares the reference with the feedback voltage and amplifies the difference to drive the output NMOS which provides load current from VIN to VOUT. Current-Limit The APL5912 monitors the current via the output NMOS and limits the maximum current to prevent load and APL5912 from damages during overload or shortcircuit conditions. Under-Voltage Protection (UVP) The APL5912 monitors the voltage on FB pin after softstart process is finished. Therefore the UVP is disable during soft-start. When the voltage on FB pin falls below the under-voltage threshold, the UVP circuit shuts off the output immediately. After a while, the APL5912 starts a new soft-start to regulate output. Thermal Shutdown A thermal shutdown circuit limits the junction temperature of APL5912. When the junction temperature exceeds +150C, a thermal sensor turns off the output NMOS, allowing the device to cool down. The regulator regulates the output again through initiation of a new softstart cycle after the junction temperature cools by 50oC, resulting in a pulsed output during continuous thermal overload conditions. The thermal shutdown designed with a 50oC hysteresis lowers the average junction temperature during continuous thermal overload conditions, extending life time of the device. For normal operation, device power dissipation should be externally limited so that junction temperatures will not exceed +125C. Enable Control The APL5912 has a dedicated enable pin (EN). A logic low signal (VEN< 0.3V) applied to this pin shuts down the output. Following a shutdown, a logic high signal re-enables the output through initiation of a new softstart cycle. Left open, this pin is pulled up by an internal current source (10A typical) to enable operation. It' not necessary to use an external transistor s to save cost. Power-OK and Delay The APL5912 indicates the status of the output voltage by monitoring the feedback voltage (VFB) on FB pin. As the VFB rises and reaches the rising Power-OK threshold (VPOK), an internal delay function starts to perform a delay time. At the end of the delay time, the IC turns off the internal NMOS of the POK to indicate the output is OK. As the VFB falls and reaches the falling Power-OK threshold (VPNOK), the IC immediately turns on the NMOS of the POK to indicate the output is not OK without a delay time.
Application Information
Power Sequencing The power sequencing of VIN and VCNTL is not necessary to be concerned. But do not apply a voltage to VOUT for a long time when the main voltage applied at VIN is not present. The reason is the internal parasitic diode from VOUT to VIN conducts and dissipates power without protections due to the forward-voltage.
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Output Capacitor The APL5912 requires a proper output capacitor to maintain stability and improve transient response over temperature and current. The output capacitor selection is to select proper ESR (equivalent series resistance) and capacitance of the output capacitor for good stability and load transient response.
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APL5912
Application Information (Cont.)
Output Capacitor (Cont.) The APL5912 is designed with a programmable feedback compensation adjusted by an external feedback network for the use of wide ranges of ESR and capacitance in all applications. Ultra-low-ESR capacitors (such as ceramic chip capacitors), low-ESR bulk capacitors (such as solid tantalum, POSCap, and Aluminum electrolytic capacitors) can all be used as an output capacitor. The value of the output capacitors can be increased without limit. During load transients, the output capacitors, depending on the stepping amplitude and slew rate of load current, are used to reduce the slew rate of the current seen by the APL5912 and help the device to minimize the variations of output voltage for good transient response. For the applications with large stepping load current, the low-ESR bulk capacitors are normally recommended. Decoupling ceramic capacitors must be placed at the load and ground pins as close as possible and the impedance of the layout must be minimized. Input Capacitor The APL5912 requires proper input capacitors to supply current surge during stepping load transients to prevent the input rail from dropping . Because the parasitic inductor from the voltage sources or other bulk capacitors to the VIN pin limit the slew rate of the surge currents. More parasitic inductance needs more input capacitance. Ultra-low-ESR capacitors, such as ceramic chip capacitors, are very good for the input capacitors. An aluminum electrolytic capacitor (>100F, ESR< 300m) is recommended as the input capacitor. It is not necessary to use low-ESR capacitors. More capacitance reduce the variations of the input voltage of VIN pin. Feedback Network
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Figure 1 shows the feedback network between VOUT, GND and FB pins. It works with the internal error amplifier to provide proper frequency response for the linear regulator. The ESR is the equivalent series resistance of the output capacitor. The COUT is ideal capacitance in the output capacitor. The VOUT is the setting of the output voltage.
VOUT
VOUT
APL5912
R1 C1 ESR C OUT R2
Figure 1
V ERR
EAMP VREF
FB
VFB
The feedback network selection, depending on the values of the ESR and COUT, has been classified into three conditions : * Condition 1 : Large ESR ( 18m ) - Select the R1 in the range of 400 ~ 2.4k - Calculate the R2 as the following:
R2(k ) = R1(k) 0.8(V) .......... (1) VOUT(V) - 0.8(V)
- Calculate the C1 as the following: VOUT(V) VOUT(V) 10 C1(nF) 40 ...... (2) R1(k ) R1(k ) * Condition 2 : Middle ESR - Calculate the R1 as the following: 1500 R1(k) = - 37.5 VOUT(V) + 30 ......... (3) ESR(m) Select a proper R1(selected) to be a little larger than the calculated R1. - Calculate the C1 as the following: COUT(uF) ................... (4) C1(pF) = [ESR(m) + 50] R1(k) Where R1=R1(selected) Select a proper C1(selected) to be a little smaller than
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APL5912
Application Information (Cont.)
Feedback Network (Cont.) the calculated C1. - The C1 calculated from equation (4) must meet the following equation :
50 37.5 VOUT(V) C1(pF) 5.1 1 + .. (5) 1 + R1(k ) ESR(m )
PCB Layout Considerations (See Figure 2) 1. Please solder the Exposed Pad and VIN together on the PCB. The main current flow is through the exposed pad. The role of VIN is a voltage sense. Refer Figure 3 to make a proximate topology. 2. Please place the input capacitors for VIN and VCNTL pins near pins as close as possible. 3. Ceramic decoupling capacitors for load must be placed near the load as close as possible. 4. To place APL5912 and output capacitors near the load is good for performance. 5. The negative pins of the input and output capacitors and the GND pin of the APL5912 are connected to the ground plane of the load. 6. Please connect PIN 3 and 4 together by a wide track or plane on the Top layer. 7. Large current paths must have wide tracks. 8. See the Typical Application - Connect the one pin of the R2 to the GND of APL5912.
VCNTL C CNTL
CIN
VCNTL VIN
Where R1=R1(calculated) from equation (3) If the C1(calculated) can not meet the equation (5), please use the Condition 3. - Use equation (2) to calculate the R2. * Condition 3: Low ESR (eg. Ceramic Capacitors) - Calculate the R1 as the following:
R1(k) = (5.9 ESR ) + 294) COUT(uF) - 37.5 VOUT(V).. (6) (m
Select a proper R1(selected) to be a little larger than the calculated R1. The minimum selected R1 is equal to 1k when the calculated R1 is smaller than 1k or negative. - Calculate the C1 as the following :
37.5 VOUT(V) C1(pF) = (0.17 ESR(m ) + 8.5) COUT(uF) 1 + .. (7) R1(k)
Where R1=R1(selected) Select a proper C1(selected) to be a little smaller than the calculated C1. - The C1 calculated from equation (7) must meet the following equation :
C1(pF) 1.25 VOUT(V) 0.033 + ESR (m ) COUT(uF) .. (8) R1 (k )
VIN VOUT
A PL5912
VOUT VOUT
Where R1=R1(calculated) from equation (6)
C OUT
C1 R1 Load R2
If the C1(calculated) can not meet the equation (8), please use the Condition 2. - Use equation (2) to calculate the R2. The reason to have three conditions described above is to optimize the load transient responses for all kinds of the output capacitor. For stability only, the Condition 2, regardless of equation (5), is enough for all kinds of output capacitor.
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FB GND
Figure 2 - Connect the one pin of R1 to the Pin 3 of APL5912 - Connect the one pin of C1 to the Pin 3 of APL5912
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APL5912
Application Information (Cont.)
Thermal Considerations See Figure 3. The SOP-8-P is a cost-effective package featuring a small size like a standard SOP-8 and a bottom exposed pad to minimize the thermal resistance of the package, being applicable to high current applications. The exposed pad must be soldered to the top VIN plane. The copper of the VIN plane on the Top layer conducts heat into the PCB and air. Please enlarge the area to reduce the case-to-ambient resistance (cCA).
102 mil
1 2
118 mil
8
3 4
SOP-8-P
7 6 5
Top VOUT plane
Ambient Air
Die
Exposed Pad
Top VIN plane
PCB
Figure 3
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APL5912
Packaging Information
SOP-8-P pin ( Reference JEDEC Registration MS-012)
E1 D1
E
H
e1 D
e2
A1
A
1 L
0.004max.
Dim A A1 D D1 E E1 H L e1 e2 1
Millimeters Min. 1.35 0 4.80 3.00R E F 3.80 2.60R E F 5.80 0.40 0.33 1.27BSC 8 6.20 1.27 0.51 0.228 0.016 0.013 4.00 0.150 Max. 1.75 0. 15 5.00 Min. 0.053 0 0.189
0.015X45
Inches Max. 0.069 0.0 06 0.197 0.118REF 0.157 0.102REF 0.244 0.050 0 . 0 20 0.50BSC 8
Copyright (c) ANPEC Electronics Corp. Rev. A.6 - Jun., 2005
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APL5912
Physical Specifications
Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
TP
(IR/Convection or VPR Reflow)
tp Critical Zone T L to T P
Ramp-up
Temperature
TL Tsmax
tL
Tsmin Ramp-down ts Preheat
25
t 25 C to Peak
Time
Classificatin Reflow Profiles
Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (T L) - Time (tL) Peak/Classificatioon Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly 3C/second max. 100C 150C 60-120 seconds 183C 60-150 seconds See table 1 10-30 seconds Pb-Free Assembly 3C/second max. 150C 200C 60-180 seconds 217C 60-150 seconds See table 2 20-40 seconds
6C/second max. 6C/second max. 6 minutes max. 8 minutes max. Time 25C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface.
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Copyright (c) ANPEC Electronics Corp. Rev. A.6 - Jun., 2005
APL5912
Classificatin Reflow Profiles(Cont.)
Table 1. SnPb Entectic Process - Package Peak Reflow Temperature s Package Thickness Volume mm 3 Volume mm 3 <350 350 <2.5 mm 240 +0/-5C 225 +0/-5C 2.5 mm 225 +0/-5C 225 +0/-5C
Table 2. Pb-free Process - Package Classification Reflow Temperatures Package Thickness Volume mm 3 Volume mm 3 Volume mm 3 <350 350-2000 >2000 <1.6 mm 260 +0C* 260 +0C* 260 +0C* 1.6 mm - 2.5 mm 260 +0C* 250 +0C* 245 +0C* 2.5 mm 250 +0C* 245 +0C* 245 +0C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0C. For example 260C+0C) at the rated MSL level.
Reliability Test Program
Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245C, 5 SEC 1000 Hrs Bias @125C 168 Hrs, 100%RH, 121C -65C~150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA
Carrier Tape
t P P1 D
Po E
F W
Bo
Ao
Ko D1
Copyright (c) ANPEC Electronics Corp. Rev. A.6 - Jun., 2005
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APL5912
Carrier Tape(Cont.)
T2
J C A B
T1
Application
A 330 1
B 62 +1.5 D
C 12.75+ 0.15 D1
J 2 0.5 Po
T1 12.4 0.2 P1 2.0 0.1
T2 2 0.2 Ao 6.4 0.1
W 12 0. 3 Bo 5.2 0. 1
P 8 0.1 Ko
E 1.750.1 t
SOP- 8/-P
F 5.5 1
1.55 +0.1 1.55+ 0.25 4.0 0.1
2.1 0.1 0.30.013
(mm)
Cover Tape Dimensions
Application SOP- 8/-P Carrier Width 12 Cover Tape Width 9.3 Devices Per Reel 2500
Customer Service
Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369
Copyright (c) ANPEC Electronics Corp. Rev. A.6 - Jun., 2005
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